Patent Documents 1 and 2 disclose an output buffer equipped with de-emphasis function in which the amplitude of an output signal emphasized when the logic of the output signal is changed, is attenuated when the logic of the output signal following the change remains unchanged. Patent document 1 discloses a configuration including a main buffer, a delay circuit, an emphasis driver, and a subtracter composed of a differential circuit. Patent Document 2 discloses an emphasis circuit constituted by a CMOS inverter, with a configuration including a tri-state buffer that performs switching control to determine whether to activate the emphasis function based on the control signal.
FIG. 8 is a diagram showing the configuration of an output buffer circuit equipped with a conventional de-emphasis function. For the sake of description, the following describes an exemplary configuration in which the ENABLE signal is introduced into the configuration (differential circuit), described in Patent Document 1, as the control signal for activating the emphasis function. Patent Documents 1 and 2 disclose an output buffer having the pre-emphasis function, which emphasizes the amplitude at the transition bit that is the first bit immediately after the logic of the signal is changed, and the de-emphasis function which decreases the emphasized amplitude when the logic of the bits following the transition bit is not changed. The following describes an output buffer with the de-emphasis function that outputs the amplitude defined by the power supply potential VDD in the transition bit and decreases the amplitude when the logic of the bit following the transition bit is not changed.
Referring to FIG. 8, the output buffer circuit comprises a pair of differential input terminals (INP/INN) that differentially receive a data signal; a main-data pre-buffer 53 that receives the differential signal input at the differential input terminals (INP/INN); a main-data main buffer 51 that receives a differential output 57 from the main-data pre-buffer 53; a delay circuit 55 that receives the differential signal input at the differential input terminals (INP/INN), delays the signal, and differentially outputs the delayed signal; a de-emphasis pre-buffer 54 that differentially receives an output 56 from the delay circuit 55; and a de-emphasis main buffer 52 that differentially receives an output 58 from the de-emphasis pre-buffer 54. The non-inverting output from the main-data main buffer 51 and the inverting output (indicated by a circle) from the de-emphasis main buffer 52 are connected in common to a non-inverting output terminal OUTP. The inverting output from the main-data main buffer 51 and the non-inverting output from the de-emphasis main buffer 52 are connected in common to an inverting output terminal OUTN. The de-emphasis pre-buffer 54 and the de-emphasis main buffer 52 become active and operable when they receive the control signal ENABLE that is active, and becomes inactive when the control signal ENABLE is inactive.
The main-data main buffer 51 and the de-emphasis main buffer 52 emphasize the amplitude of a signal for output when the signal to be output (OUTP/OUTN) undergoes the change of the logic.
When de-emphasis is disabled, the control signal ENABLE deactivates the de-emphasis main buffer 52 and the de-emphasis pre-buffer 54. In this case, the main-data main buffer 51 has a driving-capability of driving a transmission line alone (balanced transmission line connected to OUTP and OUTN).
The amplitude of the transition bit, which is the first bit signal immediately after the logic of the signal output from the main buffer 50 (OUTP/OUTN) is changed, is fixed regardless of whether de-emphasis is enabled or disabled. The waveform is emphasized by attenuating the amplitude of non-transition bits that are the signals following the transition bit. For example, when the output signal level VOH of the transition bit, generated immediately after the signal level is changed from low to high, is the power supply potential VDD and the following bit (non-transition bit) is high, the amplitude VOH of this signal is set lower than VDD. When the output signal level VOL of the transition bit, generated immediately after the signal level is changed from high to low, is the GND level and the following bit (non-transition bit) is low, the amplitude VOL of this signal is raised higher than GND.
FIG. 9 is a diagram showing an example of the configuration of the main-data main buffer 51 and the de-emphasis main buffer 52 shown in FIG. 8. In FIG. 9, the buffer 51 in FIG. 8 corresponds to a circuit 60 and the buffer 52 in FIG. 8 corresponds to circuit 61.
Referring to FIG. 9, the configuration comprises N-channel MOS transistors 62 and 63 which have sources connected in common to a constant current source I3 (current value is variably controlled) and which have gates for receiving the non-inverting signal (Main data positive) and the inverting signal (Main data negative) of the main data 57 in FIG. 8 respectively; and N-channel MOS transistors 64 and 65 which have sources connected in common to a constant current source I4 (current value is variably controlled) and which have gates for receiving the non-inverting signal (Emphasis data positive) and the inverting signal (Emphasis data negative) of the emphasis data 58 in FIG. 8 respectively. The drain of the transistor 62 and the drain of the transistor 65 are connected in common to the inverting terminal OUTN and, via a resistor R1, connected to the power supply VDD, and the drain of the transistor 63 and the drain of the transistor 64 are connected in common to the non-inverting terminal OUTP and, via a resistor R2, connected to the power supply VDD. The constant current source I4 and a switch SW are connected in series between the coupled source of the N-channel MOS transistors 64 and 65 and the ground and, when emphasis is disabled, the control signal ENABLE is inactive and the switch SW is off. The following describes the operation when emphasis is enabled (control signal ENABLE is active and switch SW is on). In the description below, a high level is a logic value 1, and a low level is a logic value 0.
When the non-inverting signal and the inverting signal of the main data 57 are 1 and 0 and the non-inverting signal and the inverting signal of the emphasis data 58 are 0 and 1 (non-inverting signal of main data 57 is the transition bit that changes from 0 to 1), the transistors 62 and 65 whose drains are connected in common are turned on, the transistors 63 and 64 are turned off, and the current corresponding to the sum of the currents of the current sources I3 and I4 flows through the resistor R1. OUTN=VDD−(I3+I4)×R1 and OUTP=VDD and the amplitude of the output signal is OUTP−OUTN=(I3+I4)×R1.
When the non-inverting signal and the inverting signal of the main data 57 are 1 and 0 and the non-inverting signal and the inverting signal of the emphasis data 58 are 1 and 0, the transistors 62 and 64 are turned on, the transistors 63 and 65 are turned off, and the currents corresponding to I3 and I4 flows through the resistors R1 and R2. Because the voltage difference between OUTP and OUTN is calculated from OUTN=VDD−R1×I3 and OUTP=VDD−R2×I4, the amplitude of the output signal is OUTP−OUTN=R1×I3−R2×I4. When R1=R2=R, OUTP−OUTN=R×(I3−I4) and the circuit in FIG. 9 becomes a subtraction circuit. The amplitude of OUTP−OUTN becomes smaller than that of the transition bit ((I3+I4)×R1), indicating that de-emphasis is performed.
When the non-inverting signal and the inverting signal of the main data 57 are 0 and 1 and the non-inverting signal and the inverting signal of the emphasis data 58 are 1 and 0 (non-inverting signal of main data 57 is the transition bit that changes from 1 to 0), the transistors 63 and 64 are turned on, the transistors 62 and 65 are turned off, and the current corresponding to the sum of the currents of I3 and I4 flows through the resistor R2. OUTP=VDD−(I3+I4)×R2 and OUTN=VDD and the amplitude of the output signal is OUTP−OUTN−(I3+I4)×R2. When the non-inverting signal and the inverting signal of the main data 57 are 0 and 1 and the non-inverting signal and the inverting signal of the emphasis data 58 are 0 and 1, the transistors 63 and 65 are turned on, the transistors 62 and 64 are turned off, and the currents corresponding to I4 and I3 flow through the resistors R1 and R2. Because the voltage difference between OUTP and OUTN is calculated from OUTN=VDD−R1×I4 and OUTP=VDD−R2×I3, the amplitude of the output signal is OUTP−OUTN=R1×I4−R2×I3. When R1=R2=R, OUTP−OUTN=R×(I4−I3) and the circuit in FIG. 9 becomes a subtraction circuit. The amplitude of OUTP−OUTN becomes smaller than that of the transition bit, indicating that de-emphasis is performed.
When emphasis is disabled, the differential circuit 61 is inactive and only the differential circuit 60 is active.
The transistors 62 and 63 of the differential circuit 60 have respective circuit sizes that can drive the transmission line only by the differential circuit 60 when de-emphasis is disabled, and the circuit size of the circuit 61 is determined by the drive current determined by the de-emphasis level.
When de-emphasis is enabled (control signal ENABLE is active), the current of the constant current source I3 of the differential circuit 60 and current of the constant current source I4 of the differential circuit 61 are the current values having the relation of a ratio determined by the de-emphasis level. When de-emphasis is disabled, the current for driving the transmission line flows only through the constant current source I3 but not through the constant current source I4.
If the circuit is configured in such a way that the amplitude of the transition bit is equal regardless of whether de-emphasis is enabled or disabled, the current is controlled so that the current value I of the sum of the constant current source I3 and the constant current source I4 when de-emphasis is enabled becomes equal to the current value I of the constant current source I3 when de-emphasis is disabled. For example, when de-emphasis is disabled (circuit 61 is inactive), the current value is variably controlled so that the constant current source I3 of the circuit 60 becomes equal to the sum value I of the constant current source I3 and the constant current source I4 when de-emphasis is enabled.
Let A be driving power (driving current, circuit size) required to drive transmission line,
B be driving power of circuit 60,
C be driving power of circuit 61, and
D be the emphasis level ([dB]) required when emphasis is enabled, we have the following equations (1) and (2):A=B  (1)D=20*log [(B−C)/(B+C)] (B>C)  (2)
Let's substitute the variables in the equations (1) and (2) with actual numeric values.
If A=120 and D=−3.5[dB], B and C are determined as B=120 and C=24 from the equations (1) and (2). The ratio of driving powers B:C between the circuits 60 and 61 becomes 5:1.
If A=120 and D=−6[dB], B and C are determined as B=120 and C=40 from the equations (1) and (2). The ratio of driving powers B:C between the circuits 60 and 61 becomes 3:1.
As described above, if the de-emphasis level is −3.5[dB] and [dB], the ratios of driving powers between the circuits 60 and 61 become 5:1 and 3:1, respectively. That is, as the de-emphasis level becomes higher, the size of the de-emphasis main buffer size becomes larger and, accordingly, the size of the pre-buffer size becomes larger.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2004-88693A
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2002-94365A